Many hardware designs contain an FPGA and a separate microcontroller. In our case of a camera design, a Xilinx Artix-7 FPGA is responsible for configuring and reading an image sensor and processing the image while the microcontroller, a Cypress FX3, provides the USB3 connectivity and application functionality.

USB3 video camera module prototype

This post discusses a variant with a single shared flash memory chip for microcontroller firmware and FPGA configuration data where the FPGA reads the bitstream in “Master SPI” mode.

Introduction

The obvious solution for storing the microprocessor firmware and the FPGA bitstream is to use two separate flash memory chips. One flash chip is…


In a recent customer project, our task was to prototype a remote control for a BLE device. The remote control should have two buttons to send a small number of commands over BLE to a host device. It should be able to run a couple of years on a small button cell.

Our initial idea was to search for a BLE controller with very low power consumption in sleep mode. We did a comparison of various controllers such as the NXP QN908x with 1µA current consumption in deep-sleep and the onsemi RSL10 which can retain the RAM content with only…


The nRF52 series of Bluetooth SoC by Nordic Semiconductor combine a powerful ARM Cortex CPU with modern Bluetooth and BLE connectivity.

Nordic provides an extensive SDK and sample code for updating the nRF52 firmware from various sources. One option is to use a PC with a serial connection and a tool called nrfutil. With nrfutil, you specify a zip file with the new firmware and a serial interface and the tool — in cooperation with the bootloader on the nRF52 — performs the actual firmware update.

Classic way of updating the firmware with nrfutil (left side) vs. alternative update mechanism from second MCU (right side)

In a recent customer project, the nRF52 was connected to a second microcontroller which…


As a side project of our DVTI camera project, we’ve built a simple EXTA based on a cheap video wall LED panel with 32 by 64 LEDs. At ESOP 2019, a couple of people have asked how this EXTA works, so we’ve decided to put this information on the web.

On the LED panel, you see a faint red border, centered around 20 by 50 pixels which compose the main are of the EXTA. Two lines below the bottom border you see a single green LED. …


In the previous part, we’ve started with the implementation of the CPU and added a first couple of instructions for branching. This time, we’ll add an ALU and a register file so that the CPU can actually perform a few useful calculations.

In the excel sheet with the instructions sorted by opcode, we find a group of instructions which are perfect candidates for our ALU and which operate on 2 registers, Rr and Rd, addressed by 5 bits (0…31):


In the first part, I’ve explained the “what” and “why” of this endeavor. Progress was slow during the past few months, not only because we had many other things going on, but also because the Vivado project had grown to a size where it took about 40 minutes from the start of a synthesis run to completing the bitstream generation for the FPGA.

A few weeks ago, I decided to change the approach. Instead of working on the full implementation, I split the project into smaller pieces. First, I recorded the output of the AD9364 for a couple of BLE…


As promised in part 2, we’re going to start with the implementation in this part of the series.

CtrlPC revisited

However, before we start, I’d like to re-visit the CtrlPC module discussed in the previous part. CtrlPC is responsible for providing the input address to the program memory for fetching instructions. I noticed two issues with the idea presented in part 2:

  • First, the CPSE instruction comes with a subtle complexity that I didn’t initially notice. The CPSE (compare-skip-if-equal) instruction compares two registers with each other, and if they are equal, skips the next instruction. The nasty thing is that “the next…


In part 1, I’ve presented the main components of the CPU, the control unit and the datapath with some first thoughts on how they may look like for an AVR core and the AVR instruction set. We’ve also seen the busing strategy options and their impact on the size and performance of the CPU to build.

Since then, I’ve had a closer look at the AVR instruction set to identify opcodes with unique register transfer sequences. …


Why?

For a recent private project, I had to extend a design based on an AVR controller with a fair amount of custom logic. As the logic is time critical and the AVR too slow to handle it, I decided to implement it in a Xilinx Spartan FPGA.

The program code that runs in the AVR is relatively small, so I thought, why not implement the AVR core in the FPGA, too? There are actually a couple of VHDL and Verilog implementations available, and I could save the AVR controller in the revised design.

When evaluating the various soft cores, I…


From time to time, we need to have a detailed look at BLE traffic. One would expect that it’s easy to find a device on the market that can monitor the whole BLE traffic at once and just dump all packets that it receives, but unfortunately, that doesn’t seem to be the case…

If we search for BLE sniffers on the web today, we can find two main categories:

  • One category contains simple single-channel sniffers that try to capture connections by following the channel-hopping (see below). The devices in this category are relatively cheap but limited in that they often…

Andreas Schweizer

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