I’ve read a lot about LoRa modulation recently but haven’t seen how an actual LoRa signal really looks like, so today, I’ve decided to set up an SDR and visualize one.
The SDR setup consists of an AD-FMCOMMS4 shield connected to a ZedBoard. The ZedBoard runs from the standard ADI SD card image.
The 868 MHz antenna is visible at the bottom right in the photo above.
A first test with the ADI IIO Oscilloscope application shows that the setup works fine. The receiver is configured to 868.2 MHz and an RF bandwidth of 400 kHz.
A manufacturer who wants to sell an electronic device in the European Economic Area is responsible for affirming the device’s compliance with the relevant EU legislation. The manufacturer puts the so-called “CE marking” on the device to declare compliance.
Interestingly, there’s no such thing as a “CE certification”. Instead, it’s the responsibility of the manufacturer (or the importer) to ensure that the device meets EU health, safety and environmental standards.
In this blog post, I will use an example (a digital video camera) to show the necessary steps before one can put the CE marking on an electronic device.
One of our projects uses a Xilinx Artix-7 FPGA. At design time, we decided to use the XC7A35T-2CSG324I, the industrial version of the XC7A35T at speed grade 2. At that time, this chip was available in large quantities from major suppliers.
Since a week or so, the project is ready for production. We asked two companies for a quote to build the boards. Both came back with the information that the FPGA is currently not available and won’t be available until October this year.
I started to look for alternatives and decided to use the pin compatible low-power version XC7A35T-L1CSG324I…
Many hardware designs contain an FPGA and a separate microcontroller. In our case of a camera design, a Xilinx Artix-7 FPGA is responsible for configuring and reading an image sensor and processing the image while the microcontroller, a Cypress FX3, provides the USB3 connectivity and application functionality.
This post discusses a variant with a single shared flash memory chip for microcontroller firmware and FPGA configuration data where the FPGA reads the bitstream in “Master SPI” mode.
The obvious solution for storing the microprocessor firmware and the FPGA bitstream is to use two separate flash memory chips. One flash chip is…
In a recent customer project, our task was to prototype a remote control for a BLE device. The remote control should have two buttons to send a small number of commands over BLE to a host device. It should be able to run a couple of years on a small button cell.
Our initial idea was to search for a BLE controller with very low power consumption in sleep mode. We did a comparison of various controllers such as the NXP QN908x with 1µA current consumption in deep-sleep and the onsemi RSL10 which can retain the RAM content with only…
The nRF52 series of Bluetooth SoC by Nordic Semiconductor combine a powerful ARM Cortex CPU with modern Bluetooth and BLE connectivity.
Nordic provides an extensive SDK and sample code for updating the nRF52 firmware from various sources. One option is to use a PC with a serial connection and a tool called nrfutil. With nrfutil, you specify a zip file with the new firmware and a serial interface and the tool — in cooperation with the bootloader on the nRF52 — performs the actual firmware update.
In a recent customer project, the nRF52 was connected to a second microcontroller which…
As a side project of our DVTI camera project, we’ve built a simple EXTA based on a cheap video wall LED panel with 32 by 64 LEDs. At ESOP 2019, a couple of people have asked how this EXTA works, so we’ve decided to put this information on the web.
On the LED panel, you see a faint red border, centered around 20 by 50 pixels which compose the main are of the EXTA. Two lines below the bottom border you see a single green LED. …
In the previous part, we’ve started with the implementation of the CPU and added a first couple of instructions for branching. This time, we’ll add an ALU and a register file so that the CPU can actually perform a few useful calculations.
In the excel sheet with the instructions sorted by opcode, we find a group of instructions which are perfect candidates for our ALU and which operate on 2 registers, Rr and Rd, addressed by 5 bits (0…31):
In the first part, I’ve explained the “what” and “why” of this endeavor. Progress was slow during the past few months, not only because we had many other things going on, but also because the Vivado project had grown to a size where it took about 40 minutes from the start of a synthesis run to completing the bitstream generation for the FPGA.
A few weeks ago, I decided to change the approach. Instead of working on the full implementation, I split the project into smaller pieces. First, I recorded the output of the AD9364 for a couple of BLE…